Summary
Overview
Work History
Education
Skills
Languages
Accomplishments
MANAGEMENT SKILLS
Timeline
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LAKSHMI SHOWJANYA KONETI (BELGIUM WORK VISA READY)

LAKSHMI SHOWJANYA KONETI (BELGIUM WORK VISA READY)

LEUVEN

Summary

Senior Physical Design Engineer with 10 years of experience in placement, floor planning, clock tree synthesis, and static timing analysis. Proven track record in successful tapeouts, team mentorship, and design optimization for performance and power efficiency. Skilled in Tcl and Perl scripting, complemented by strong project management capabilities ensuring high-quality deliverables.

Overview

14
14
years of professional experience

Work History

STAFF PHYSICAL DESIGN ENGINEER

CYIENT SEMICONDUCTORS INDIA PVT LTD
HYDERABAD
12.2024 - Current
  • Mentored junior engineers on design techniques and project execution.
  • Created floor plans with high utilization of area, power and performance goals.
  • Analyzed design data to ensure efficient implementation of complex designs.
  • Participated in chip bring up activities by debugging critical path failures at top level and submodule levels.
  • Performed static timing analysis on blocks and full-chip level using PrimeTime or similar STA tools.
  • Utilized scripting languages such as Tcl and Tk, Perl to automate the flow of tasks in the physical design process.
  • Evaluated new technologies related to Physical Design flows and developed solutions for them.
  • Optimized synthesis results to meet timing constraints and power budgets.

STAFF PHYSICAL DESIGN ENGINEER

AMD INDIA PVT LTD
HYDERABAD
08.2020 - 12.2024
  • Worked on MI300,MI350,MI400 and MI450 critical SP tiles.
  • Collaborated with cross-functional teams to optimize design processes and workflows.
  • Managed design documentation to maintain accurate project records and revisions.
  • Lead SP tiles and team of junior engineers on physical design methodologies and tools usage.
  • Worked on different floor plans to meet area, power and performance goals.
  • Performed static timing analysis on blocks and full-chip level using PrimeTime or similar STA tools.
  • Tried different Optimization techniques at synthesis to meet timing constraints and power budgets.
  • Carried out ECOs by analyzing schematic changes and performing necessary modifications in the existing layout.
  • Fixed critical conformal ECO in time and received good appreciation for our team.
  • Utilized scripting languages such as Tcl and Tk, Perl, Python to automate the flow of tasks in the physical design process.
  • Participated in chip bring up activities by debugging critical path failures at top level and submodule levels.
  • Coordinated with back-end designers for placement and routing activities like congestion avoidance and DRC and LVS checking.

SENIOR PHYSICAL DESIGN ENGINEER

CERIUM SYSTEMS SDN BHD , MALAYSIA
PENANG
05.2018 - 06.2020
  • Technology: Intel 10nm
  • Client: Intel
  • Duration: April 2018 to April 2019
  • Tools: IC compiler, IC compiler II, Prime Time, Calibre.
  • Responsibilities: P&R flow Floor plan to GDS-II for 2 PNR tiles with count 1200k
  • Challenges: Couple of floorplans for better timing.
  • Reduced noise and transition violations.
  • Responsible for fixing critical timing and RV violations.

SENIOR PHYSICAL DESIGN ENGINEER

SoCtronics Technologies Pvt Ltd, Hyderabad
Hyderabad
02.2015 - 05.2018
  • Technology: TSMC 7nm,14nm,16nm Finfet ,GF 22FD-SOI, 14LPP
  • Advanced Micro Devices flow and SoCtronics flow
  • Lead a group of four engineers
  • Tools: SYNOPSYS : ICC1, ICC2,Fusion Complier Prime Time, CADENCE: Innovus,SoC Encounter,Tempus,Voluts=Fi, Mentor Graphics : Calibre.
  • Responsibilities: Complete P&R flow floorplan to GDS-II and ECO.
  • Logic complexity upto 2M gates with max 2GHz clocks.
  • Challenges: Placement congestion, Clock tree balancing, Critical Timing,SI Timing fixes, ECO fixes, DRC,LVS DPT fixes,EMIR, Sign off fixes.
  • Worked on Analog layouts: developed layouts for PLL and its sub blocks.
  • Challenges : Mactiching in VCO, shealding, EMIR, DRC, LVS, Metal filling for symmetry.

Physical Design Engineer Trainee

Vedall IT, Hyderabad
Hyderabad
08.2014 - 01.2015
  • Analog Layout Projects:
  • Technology: GF- 22FDSOI and 14LPP.
  • Responsibilities: Developed layouts for PLL (sub-blocks, integration), CTX_top, High speed transmitter (sub-blocks, integration) Charge pump, VCO, Feedback divider, Input divider, cross-equalizer.
  • Challenges: Matching critical devices, Shielding, EMIR, DPT, DRC, LVS, Manual metal filling for symmetry.

Assistant Professor in ECE Department

Geethanjali Engineering College, Hyderabad, India
Hyderabad
01.2012 - 01.2014

Education

M.Tech - Embedded System Design

JNTU
Kakinada, Andhra Pradesh, India
01.2012

B.Tech - Electronics & Communications

JNTU
Kukatpally, Andhra Pradesh, India
01.2008

Skills

  • Floor Planning
  • Placement
  • Clock Tree Synthesis and optimization
  • Routability Analysis and optimization
  • Static Timing Analysis and Timing Closure
  • Cross Talk Analysis
  • Physical Verification DRC, LVS, DFM, ERC
  • Analog layout Development
  • Matching Techniques
  • Shielding
  • EM / IR
  • Perl, Tcl, Skill
  • Team mentoring
  • Attention to detail
  • Project management

Languages

English, Hindi, Telugu

Accomplishments

  • Received AMD MI300 project issues resolving aprreciation
  • I was given a lead role in short time based on my performance and execution of projects with AMD client.

MANAGEMENT SKILLS

  • Project management
  • Organizing skills
  • Ability to work under pressure
  • Self-motivation
  • Team work
  • Effective Communication
  • Curious to learn

Timeline

STAFF PHYSICAL DESIGN ENGINEER

CYIENT SEMICONDUCTORS INDIA PVT LTD
12.2024 - Current

STAFF PHYSICAL DESIGN ENGINEER

AMD INDIA PVT LTD
08.2020 - 12.2024

SENIOR PHYSICAL DESIGN ENGINEER

CERIUM SYSTEMS SDN BHD , MALAYSIA
05.2018 - 06.2020

SENIOR PHYSICAL DESIGN ENGINEER

SoCtronics Technologies Pvt Ltd, Hyderabad
02.2015 - 05.2018

Physical Design Engineer Trainee

Vedall IT, Hyderabad
08.2014 - 01.2015

Assistant Professor in ECE Department

Geethanjali Engineering College, Hyderabad, India
01.2012 - 01.2014

M.Tech - Embedded System Design

JNTU

B.Tech - Electronics & Communications

JNTU

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LAKSHMI SHOWJANYA KONETI (BELGIUM WORK VISA READY)