Cheng Wang

• 2021.04~until now

High Speed Simplified Coherent Receiver Design from System to Circuit for Beyond 50G PON in Optical Communication.

>> Verifying system idea by measurement using PIC (photonic integrated chip) and EIC (electrical integrated chip) designed in our lab.

(Paper published on ECOC2023-oral presentation as First Author)

>> Joint Experiment with Orange Company for 50G Burst Mode PON.

(Published on ECOC2023-poster as Equivalent Contributed Author)

>> Will design new version of high speed burst mode TIA(Target at 100Gb/s Burst Mode) for my simplified coherent receiver. Already accumulated high speed continuous mode TIA design experience.

• 2021.04~2022.03

224GS/s 1-to-4 ADC Sampling Front-end with Over 67GHz Bandwidth Using 50% duty-cycle Clocks in 130nm SiGe IHPG2CU process. Mainly be responsible for clock path design for high speed samplers.(paper submitted for 2024 CICC as Third Co-Author)

• 2022.03~2022.06

DCOC Loop and nonlinear function design in High Speed TIA in 55nm ST BiCMOS Process. (Assistant other senior PhD's Project)

• Analog IC design for Security Chip

Mainly be responsible for basic analog deisgn block-Opamp, Oscillator(500nW ultral low power RC600K Oscillator), Bandgap and LDO.